Metal width from I/O pad to ESD devices should be at least:
Metal1 ? ? ? ? ? ? ? ? ? ? 10 um
Metal2– Metal5 ? ? 10 um
MetalTop ? ? ? ? ? ? ? ? 10 um
Contacts and vias in the ESD current path should be at least:
Contact ? ? ? ? ? ? ? ? ? 50
Via1 ? ? ? ? ? ? ? ? ? ? ? ? ?30
Via2 – Via4 ? ? ? ? ? ?30
Top Via ? ? ? ? ? ? ? ? ? ?30
14.6.2 ? ? Design Guidelines for NMOS FETs Connected to I/O Pad
14.6.2.1 Maximum finger gate width is 40 um (recommended 10-25 um). Minimum total finger
width used in I/O buffer is 400 um.
14.6.2.2 Minimum drawn gate length for transistors in I/O buffer is 0.40 um for thick oxide
transistors and 0.24 um for thin oxide transistors. Poly linewidth for each finger in multifinger transistors must be the same.
14.6.2.3 Recommended
draincontact to gate spacing (DCGS) for silicide-blocked drain is 2.0 um
(2.08 um for 1.8V device), where minimum silicided-block to gate edge spacing is 1.78 um
(1.86 um for 1.8V device). Refer to section 14.6.2.11 for various options of laying out
salicide block.
14.6.2.4 Recommended
sourcecontact to gate spacing (SCGS) with salicide-blocked is 0.70 um
(0.48 um for 1.8V device), where recommended silicided-block to gate edge spacing is 0.48
um (0.26 um for 1.8V device). Refer to section 14.6.2.11 for various options of layout out
salicide block.
14.6.2.5 Ensure uniform current flow across the entire width of FET. Avoid using fingers with
different widths. Maximize the number of contacts along entire width based on
electromigration rule. Non-orthogonal and serpentine poly gates are not allowed in the I/O
buffer.
14.6.2.6 Double guard ring structure must be placed around protection circuit to improve latch-up
immunity. No other active circuitry is allowed inside or between such guard rings.
14.6.2.7 Minimum Composite overlap of contact for diffusion connected to pad is 1.0 um.
14.6.2.8 Rounded/Beveled corner is recommended for all diffusions along the ESD discharge path to
reduce electric field at the corners.
14.6.2.9 Minimum spacing of 15 um must be added between I/O pad NCOMP to nearby Ground
NCOMP or from a Vdd NCOMP to Ground NCOMP.
14.6.2.10 For multi-finger FETs in the ESD path, layout must be done to make sure that each finger
sees identical resistance in the ESD current path. This requires identical layout of fingers
(width and poly lengths) and current must enter from one side and leave from the other side
in the array of fingers.
