PN序列生成器的基本結(jié)構(gòu)為LFSR(linear feedback shift register)，在通信領(lǐng)域PN序列可作為測(cè)試數(shù)據(jù)源或者擾碼生成器使用?；拘畔⒑徒Y(jié)構(gòu)可參考 Matlab中的PN序列產(chǎn)生模塊說明

pn_sequence_setupex.png

上圖中，按照Matlab定義，對(duì)應(yīng)的生成多項(xiàng)式為z^6+z+1,即[6 1 0]，或者[1 0 0 0 0 1 1]

參考生成代碼

[17 3 0]生成matlab代碼（標(biāo)準(zhǔn)參考為[17 14 0]）

%% serial for PN17 [17,3,0]
pn = ones(1,17);
N = 2^17-1;
M = 2*N;
for i=1:M
    outpn(1,i) = pn(17);
    pn17 = pn(17);
    pn14 = pn(14);
    pn(17:-1:2) = pn(16:-1:1);
    pn(1) = xor(pn17, pn14);
end

上面生成的PN17周期應(yīng)為2^17-1

% verify the period of PN seq 
equRcrd = 1;
for k = 1:N
    if outpn(k) ~= outpn(k+N) 
        equRcrd = 0;
    end
end
equRcrd

遍歷性（部分的，全遍歷時(shí)間太長）

% Traversal
% only for 1:100, due to the long running time
% you can change the traversal range 
ofst = 1000;
for i=(1+ofst):(10+ofst) %N-17
    cnt(i)=0;
    for k=(i+1):N-16
        if outpn(i:i+16) == outpn(k:k+16)
            cnt(i) = cnt(i)+1;
        end
    end
end
max(cnt)

并行8路[17 3 0] (輸出為小端 little endian)

pn_p8 = ones(1,17);
N_p8 = 2^17/8;
for i=1:N_p8
    outpn_p8(:,i) = pn_p8(17:-1:10);
    pn_p8_copy = pn_p8;
    pn_p8(17:-1:9) = pn_p8(9:-1:1);
    pn_p8(8:-1:1) = xor(pn_p8_copy(17:-1:10),pn_p8_copy(14:-1:7));
end

VHDL代碼， 并行8路 (輸出為小端 little endian)

d_output(7) <= pn17_pd(10); 
d_output(6) <= pn17_pd(11);
d_output(5) <= pn17_pd(12);
d_output(4) <= pn17_pd(13);
d_output(3) <= pn17_pd(14);
d_output(2) <= pn17_pd(15);
d_output(1) <= pn17_pd(16);
d_output(0) <= pn17_pd(17);

pn17_pd(17 downto 9) <= pn17_pd(9 downto 1);
pn17_pd(8 downto 1)  <= pn17_pd(17 downto 10) xor pn17_pd(14 downto 7);

對(duì)于上述8路并行代碼，采用此種簡潔形式的前提是滿足17-3-8 >= 0，否則生成代碼會(huì)復(fù)雜