參考《FPGA Prototyping By Verilog Examples》

module vga_sync

(

input clk,reset,

output hsync,vsync,video_on,p_tick,

output[9:0] pixel_x,pixel_y

);

//VGA 680*480

localparam HD=640;

localparam HF=48 ;

localparam HB=16 ;

localparam HR=96 ;

localparam VD=480;

localparam VF=10 ;

localparam VB=33 ;

localparam VR=2? ;

//mod-2 counter

reg mod2_reg;

wire mod2_next;

wire pixel_tick;

always@(posedge clk,posedge reset)

if(reset)

mod2_reg<=0;

else

mod2_reg<=mod2_next;

assign mod2_next=mod2_reg+1;

assign pixel_tick=mod2_reg;//

//hsync counter

reg [9:0]h_count_reg;

wire [9:0]h_count_next;

always@(posedge clk,posedge reset)

if(reset)

h_count_reg<=0;

else

h_count_reg<=h_count_next;

assign h_end=(h_count_reg==799);

assign h_count_next=pixel_tick? ((h_end)?0:(h_count_reg+1)) :? (h_count_reg);

assign pixel_x=h_count_reg;

//vsync counter

reg [9:0]v_count_reg;

wire [9:0]v_count_next;

wire h_end,v_end;

always@(posedge clk,posedge reset)

if(reset)

v_count_reg<=0;

else

v_count_reg<=v_count_next;

assign v_end=(v_count_reg==524);

assign v_count_next=pixel_tick&&h_end? ((v_end)?0:(v_count_reg+1)) :? (v_count_reg);

assign pixel_y=v_count_reg;

//output buffer

reg h_sync_reg,v_sync_reg;

wire h_sync_next,v_sync_next;

always@(posedge clk,posedge reset)

if(reset)

begin

h_sync_reg<=0;

v_sync_reg<=0;

end

else

begin

h_sync_reg<=h_sync_next;

v_sync_reg<=v_sync_next;

end

assign? h_sync_next=~(h_count_reg>=(HD+HB)&&h_count_reg<=(HD+HB+HR-1));

assign? v_sync_next=~(v_count_reg>=(VD+VB)&&v_count_reg<=(VD+VB+VR-1));

//output

assign video_on=(h_count_reg